1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and an electric device with the same.
2. Description of Related Art
Currently known EEPROMs are mostly formed of memory cells floating gates of which store data charge. Arranging NAND cell units each having a plurality of memory cells connected in series, a cell array of a NAND-type flash memory which is known as one of the EEPROMs is constructed. Source and drain diffusion layers of the memory cells in the NAND cell unit are shared with adjacent cells. To increase the capacity of the NAND-type flash memory, it is effective to increase the number of cells in the NAND cell unit, thereby increasing the capacity of a block defined as a group of a plurality of NAND cell units sharing a word line with them. Since one block is serves as a unit for data erasing at a time, increasing the block capacity, the data erase unit of the NAND-type flash memory becomes large.
If only small capacity data is written in such a large block of the NAND-type flash memory, the remaining area of the block becomes wasteful. In consideration of this point, in practice, one block is often divided into a few or several areas, and data control is performed by each area. However, using the above described erasing scheme in which a block is adapted to a data erase unit, it takes an extra time for data rewriting. In detail, assume, for example, that a data A area and data B area are defined in a block. In order to replace the data A by data C, it is required to do at least one block erase operation and write operations of data A and C. That is, as a result of that the entire block is erased prior to data C writing, it is necessary to write the data A again. This brings an overhead time in data processing.
To decrease such the overhead time in the data rewriting operation, it is effective to do a data erase operation by every word line (i.e., page). Such a selective data erase (i.e., page erase) may be done by setting word lines in a non-selected area at a floating state, applying 0V to word lines in a selected area, and applying a erase voltage to a p-type well on which the cell array is formed. Under such the condition, stored charge of the respective floating gates is discharged to the channel by FN tunneling in the memory cells in the selected area, whereby an erase state with a low threshold voltage (i.e., data “1” state) is obtained in every selected cell. In the non-selected area, the word lines (i.e., control gates), which are in a floating state, are boosted by capacitive coupling in accordance with increasing of the erase voltage applied to the p-well to be an “erase-inhibition” state. Therefore, by use of such the erase method, it becomes possible to do data write for only a selected area in a block, which is required to be rewritten. Such the erase method has already been provided in, for example, Japanese Patent Application (kokai) No. 10-302488 and U.S. Pat. No. 6,107,658.
However, in the above described selective erase method, there is a problem that the erase-inhibition states in the non-selected area are not uniform, and a large erase stress is applied to a cell adjacent to the selected area. This situation will be explained in detail referring to FIGS. 9 and 10. These show voltage relationships in a NAND cell unit in a selective data erase mode. In these figures, word lines WL0–3 are selected pages, and word lines WL4–7 are non-selected pages. FIG. 9 shows a state just before the erase voltage Vera(=20V) application. In this state, non-selected word lines WL4–7 are precharged to Vdd−Vtn (Vtn: threshold voltage of a transfer transistor for transferring a word line driving voltage) to be floating.
In this state, applying the erase voltage Vera to the p-type well, the voltage relationships of FIG. 10 are obtained. In the non-selected area, word line WL4 adjacent to a selected word line becomes to be a floating state of Vdd−Vtn+βVera (β: coupling coefficient), while the remaining non-selected word line WL5–7 to be a floating state of Vdd−Vtn+αVera (α: coupling coefficient). The coupling coefficients β and α have a relationship of β<α. The reason of this will be explained bellow referring to FIG. 11.
As shown in FIG. 11, giving attention to a memory cell selected by a word line WLi, the coupling coefficient is defined by coupling capacitances C1 to C4 of the floating gate and control gate and voltages thereof. The word line WL4 in the non-selected word lines WL4–7 is adjacent to a selected word line WL3 to which 0V is applied. As a result, the voltage boost of the word line WL4 is more suppressed in comparison with other non-selected word lines WL5–7, whereby the relation ship of β<α will be obtained. In other words, one of the non-selected word lines, which is adjacent to a selected word line, is not boosted to a sufficient high voltage. As a result, in each of memory cells along such a word line, the voltage between the control gate and the p-type well becomes large, whereby a large erase stress is applied to the memory cells.
In FIG. 11, the coupling capacitance C1 between word lines in the parasitic capacitances of a word line tends to become large as miniaturizing the cell array. Therefore, performing the above described selective erase operation every word line, a large erase stress is applied to cells along a non-selected word line adjacent to a selected word line. This results in that the number of erase operations is limited, or such a case may occur that the erase operation becomes impossible.